DSP SW Engineer

Own the implementation and evaluation of defined DSP and 5G NR physical-layer (PHY) functions for satellite communications over non-terrestrial networks (NTN), working from agreed specifications and technical guidance.

Develop and run PHY/link-level simulations to measure error rates, throughput, and acquisition and tracking performance under representative satellite channel conditions, including propagation delay, Doppler, noise, and RF impairments.

Develop, test, and optimize C/C++ DSP firmware for 5G NR PHY processing, meeting defined execution-time, memory, power, and numerical-accuracy requirements.

Create floating-point and fixed-point reference models, reproducible test vectors, and expected results for ASIC designers and verification engineers. Document interfaces, scaling, rounding, saturation, and other assumptions needed to compare implementations.

Contribute to SystemC transaction-level modeling (TLM) and high-level synthesis (HLS) development, including synthesizable implementations, with guidance from engineers experienced in these flows.

Support pre-silicon verification and new-chip bring-up by running regressions, comparing model, firmware, and hardware results, investigating discrepancies, and documenting fixes with ASIC, verification, and software engineers.

Demonstrated DSP and digital-communications fundamentals, including sampling, filtering, modulation, OFDM, synchronization, channel estimation, and error-correction concepts. Evidence may come from academic, research, personal, or professional projects.

Ability to implement and debug numerical algorithms in C/C++, and to use Python or MATLAB for simulation, analysis, and test automation.

Working knowledge of wireless PHY processing and the ability to translate technical specifications into implementation and test cases; familiarity with the basic structure of a 5G NR PHY.

Understanding of fixed-point arithmetic, quantization, overflow, and numerical precision, with the ability to compare an implementation against a reference model.

Understanding of embedded software constraints, including execution time, memory use, and hardware/software interfaces, supported by practical implementation or debugging work.

Ability to build reproducible tests, use version control, document technical assumptions and results, and explain discrepancies during code and design reviews.

Experience with SystemC TLM, or with HLS tools to develop and verify synthesizable C/C++ or SystemC implementations.

Experience with 5G NR or NTN algorithms and specifications, satellite channel modeling, or compensation for Doppler and timing effects.

Experience with FPGA/ASIC verification, emulation, SDR platforms, chip bring-up, or laboratory validation of communication systems.

Experience with 5G NR MAC, PHY/MAC interfaces, scheduling interactions, or HARQ procedures.

Experience implementing and optimizing algorithms on vector DSPs, including SIMD intrinsics, vectorization, and efficient memory access.

Experience with low-power ASIC or firmware design, including reducing computation and data movement, managing idle states, or measuring power consumption.